1. Field of the Invention
The present invention relates to a semiconductor memory device having an insulated gate field effect transistor (hereinafter referring to as MISFET) as a fundamental element.
2. Description of the Prior Art
FIG. 1 is a plane view of the conventional semiconductor memory device. FIG. 2(a) is a sectional view taken along the A--A' line of FIG. 1, and FIG. 2(b) is an equivalent circuit diagram thereof. In the drawings, the reference (1) designates a P type semiconductor substrate; (2) designates a low resistant P type semiconductor region which is selectively formed on one main surface of the P type semiconductor substrate (1) to separate an electrical connection between MISFET; (3) and (4) respectively designate N type semiconductor region for m th and m+1 th bit lines (5) designates a first layer of polycrystalline silicon for one electrode of MIS capacitors (n) and (n+1) (FIG. 2(b)); (6) designates a second layer of polycrystalline silicon for switching transistors (l) and (l+1) (FIG. 2(b)); (7) designates a contact hole for electrical connection between the second layer of polycrystalline silicon and an aluminum wire (8) as a word line; and (9) designates an oxide layer.
The operation of the conventional semiconductor memory device having said structure will be illustrated. The m th bit string will be especially illustrated.
When the aluminum wire (8) as the word line is at a high potential, the switching transistors (l) and (l+1) are in the ON state. In this case, if the m th bit line is at a high potential, high potential charge is charged in the MIS capacitor (n) whereas if it is at a low potential, a low potential charge is charged. In this case, the first layer of polycrystalline silicon (5) serving as one of the electrode MIS capacitor (n) is biased at the highest potential for the memory device. Then, if the potential of the aluminum wire (8) serving as the word line is reduced to a low potential, preferably zero volt, the switching transistor (l) is changed in the OFF state to memorize the potential charged to the MIS capacitor (n). This results in write-in and storage of the data for memory.
The read-out of the data will be carried out as follows.
When the aluminum wire (8) as the word line is changed to a high potential, the following potential change is given in the m th bit line. ##EQU1## wherein Cs designates the capacity of the MIS capacitor (n); Cb designates the capacity of the m th bit line Vs designates the memorized potential; and Vp designates an original potential of the bit line and V designates a changed potential of the bit line; and .DELTA.V designates a difference of potentials from the potential Vp. If Vs=OV in the memory condition of the data, the following equation is given: ##EQU2##
If Vs=Vcc, the following equation is given: ##EQU3## wherein Vcc designates a high potential, as Vcc&gt;&gt;Vp.
The read-out potential difference from Vs=0 and Vcc is given by the equation: ##EQU4##
The value is the read-out signal to discriminate "1" or "0" for the data. The fine potential such as .DELTA.V.sub.1 -.DELTA.V.sub.0 =0.25V in the event that Vcc=5V and Cb/Cs=19 is amplified by an amplifier connected to the bit line and the data are taken out of the semiconductor memory device.
Thus the conventional semiconductor memory device has the following disadvantages.
(A) The bit line capacity (Cb) formed by connection of the N type semiconductor, the substrate and is usually large whereby Cb/Cs is large resulting in a small read-out potential difference given by the equation (4).
(B) The bit line is made of PN junction. For example, if .alpha.-rays from the package are applied to the bit line, electrons generated are stored in the bit line to vary the potential of the bit line to cause an erroneous operation.
(C) The gate length of the switching transistors (l) or (l+1) is different depending upon production tolerances.